In conventional analog/digital converters having a successive-approximation architecture of the charge-redistribution type, providing a network of capacitors requires the implementation of an array of capacitors. The number of capacitors in the array depends on the number of bits used to express the digital code in output from the successive-approximation converter. In particular, the capacitive array is implemented for the digital/analog converter that is present in the A/D successive-approximation converter. The capacitive values of the various capacitors must be such that one is twice the other. The structure that is generally used is the common-centroid type.
The value of the capacitance between a capacitor associated with one bit and the capacitor associated with the adjacent bit must be scaled precisely by a factor of 2 in order to achieve good binary encoding in output. The capacitor array, however, entails problems due to parasitic effects which are inevitably linked to capacitive couplings among the various layers by means of which the capacitors are formed. In particular, parasitic effects occur due to capacitive coupling between the edges of the facing plates of the capacitor. If these parasitic capacitances are not compensated by a particular structure of the array, said capacitances can have a negative effect because they vary the value of the ratio among the capacitive values.
In practice, the parasitic capacitances cause the ratio between a capacitor and the adjacent one to be other than a factor of 2. The ratio in fact increases due to the addition of an offset arising from the parasitic capacitance. This leads to a change in the width of the conversion channel and therefore to an altered binary code in output. Providing the capacitors of the array by means of a parallel connection of unitary capacitors solves this problem of parasitic capacitance altering the ratio.
The parasitic capacitive effects are also present as capacitive edge effects between the perimetric edge of a capacitor and the capacitors that are adjacent thereto. These last capacitive effects cause the ratio between one capacitor and the adjacent one in the above-described capacitive array to be other than the intended ratio of 2, because these parasitic capacitances cannot be compensated by conventional array structures.
FIG. 3 illustrates a conventional capacitor array in which the thicker lines represent the connections between the capacitors 1A which are parallel-connected and the reference numerals 10 designate the parasitic capacitances caused by capacitive edge couplings among adjacent capacitors. The figure shows that the capacitor 1A in the bottom left region of the illustrated mini-array has three parasitic capacitances 10, one for each free side, while the capacitor 1A which is adjacent thereto in an upward region instead has two parasitic edge capacitances 10 and therefore a capacitive imbalance is present.